To facilitate a head start in camera design-in with LS2G, we offer to your attention our evaluation platform an GUI. Our evaluation platform features a connector base suited to the LS2G family, while it also bases on a pragmatic digital readout electronics base with the Kintex 7 FPGA family.


The primary image out interface of our LS2G evaluation board is based on the Camera link Base/Medium/Full configuration. Additionally the board supports a PCI-Express x4 interface which can be reconfigured for custom use.
Brief specification sheet
Supported sensors | LS2G-6K, LS2G-12K, LS2G-16K | LVDS Channels | 130 | Flash | 64 MB |
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Connector base | KEL DT01-240S-TR-T | LVDS Channel speed | 1.28 Gbit/sec | Reference Clock | low-jitter 50 fs RMS 100MHz and 26 MHz crystal oscillator Si5332 PLL chip |
FPGA | Xilinx Kintex 7 – XC7A160T – XC7A410T |
Governor MCU | ATMega 2560 | Supported sensor supply voltages |
3.3 V (pixel) 3.3 V (anacore) 1.5 V (dig) 1.5V (lvds) |
Camera Link variants supported | Base Medium/Full Deca |
Control IO | UART/FIFO/JTAG/SPI/I2C | GPIO | 8x (3.3V tol)
8x (1.8V tol) |
High-speed IO | GTX transceiver base PCI-express protocol |
Control IO chip | FT2232HQ | Power | 24V, 25W |
To obtain mode detailed information about our evaluation platform, please contact us.
Sensor control Graphical User Interface (GUI)
Along with the evaluation board, we provide a supporting GUI to control LS2G. The GUI can operate the sensor in internal self-triggered mode which is primarily intended for sensor evaluation, or alternatively we can supply an external triggered control for slow scan image capture via the Camera Link interface.


Reference FPGA design project
We offer a reference FPGA design for the LS2G sensor family based on our evaluation platform. The reference project includes a deserialization mechanic with dynamic phase alignment of the LVDS interface of LS2G.
